05/05/2021

Hardware Implementation of Fully Pipelined Turbo Decoders


  • ORGANISATION/COMPANY
    IMT Atlantique
  • RESEARCH FIELD
    Computer scienceInformatics
    EngineeringCommunication engineering
  • RESEARCHER PROFILE
    First Stage Researcher (R1)
    Recognised Researcher (R2)
    Established Researcher (R3)
    Leading Researcher (R4)
  • APPLICATION DEADLINE
    17/06/2021 00:00 - Europe/Brussels
  • LOCATION
    France › Brest
  • TYPE OF CONTRACT
    Temporary
  • JOB STATUS
    Full-time
  • OFFER STARTING DATE
    01/09/2021

OFFER DESCRIPTION

Building on initial results on the hardware implementation of new decoding algorithms for Turbo decoding, the ANR funded JCJC project “TurboLEAP”, which is set to start 01.03.2021 and led by Stefan Weithoffer, will investigate the design of ultra-high throughput hardware architectures for the decoding of Turbo codes, focusing mainly on hardware design aspects. Within TurboLEAP, the PhD candidate is expected to play a significant role in the original approach applied traditionally by the members of the Mathematical and Electrical Engineering (MEE) department of IMT Atlantique consisting of a close interaction between Silicon and Algorithm design. Contrary to classical procedures, in this approach, algorithms are thought and derived from the start to consider at equal footing the hardware implementation and performance related constraints. Indeed, the candidate is expected to explore the full potential of fully pipelined iteration unrolled Turbo decoder hardware architectures. Throughputs of more than 1 Tb/s for large frame sizes with several thousands of information bits are targeted. Furthermore, decoder hardware architectures for Spatially coupled Turbo codes shall be investigated.



Funding category: Financement public/privé



PHD Country: France

More Information

Offer Requirements

Specific Requirements

The candidate should hold a Master degree or an engineering degree in digital communications. The following
qualifications are beneficial for the completion of the project:

  • Experience with one or more of the following languages: C, C++, Python
  • Experience with one of the following hardware description languages: VHDL, Verilog, SystemC
  • Experience with hardware development on FPGA and/or ASIC
  • Advanced lectures on channel coding and communication systems

Map Information

Job Work Location Personal Assistance locations
Work location(s)
1 position(s) available at
IMT Atlantique
France
Brest

EURAXESS offer ID: 636545
Posting organisation offer ID: 97990

Disclaimer:

The responsibility for the jobs published on this website, including the job description, lies entirely with the publishing institutions. The application is handled uniquely by the employer, who is also fully responsible for the recruitment and selection processes.

 

Please contact support@euraxess.org if you wish to download all jobs in XML.